1. Field of the Invention
The present invention relates to programmable logic arrays for performing high speed operations.
2. Description of the Prior Art
Programmable logic arrays (PLA) incorporated in different logical LSIs, such as microprocessors, and used for control circuits and decoders are mainly divided into two categories: NOR type PLAs having an array area constructed by transistors arranged at each intersection of orthogonal wiring leads and NAND type PLAs having an array area constructed by transistors connected in series, respectively.
FIG. 1 indicates the construction of a conventional NAND type PLA having three sets of cell arrays consisting of N-channel FETs (which are referred to hereinafter as NFETs) connected in series and conductively controlled by input signals IN1 through IN6 or their inverted signals so as to produce logical product output signals OUT1 through OUT3 corresponding to each of the arrays.
Among the three sets of arrays, the cell array block 1 comprises NFETs 3, . . . 3 connected in series with each other and the number of these NFETs is the same as that for the input terminals, which are conductively controlled by the input signals IN1 through IN6 applied to the input terminals or their inverted signals. One terminal of the NFETs is connected to a ground and the other terminal of the NFETs is connected to a power supply V.sub.cc on one side through a P-channel FET5 (which is referred to hereinafter as PFETs) which is always rendered conductive, and to the input terminal of an inverter 7 on the other side.
The output of the cell array block 1 is inverted by the inverter 7 and the following logical product output signal OUT3 is produced from the inverter 7: EQU OUT3=IN1 . IN2 . IN3 . IN4 . IN5 . IN6
In the manner described, the NAND type PLA is constructed by a plurality of FETs connected in series so as to produce each of the inverted output signals as logical product outputs.
In this circuit, when all of the FETs (Field Effect Transistors) in series are rendered conductive, a current path is formed. However, the total ON-type resistance of the FETs becomes large because of the series connected FETs and steady current is restricted to low levels. As a result, there is the advantage that the circuit can be operated at low power consumption.
On the other hand, for the NAND type PLA, when formed in an integrated-circuit, its layout can be realized within a smaller area compared with the NOR type PLA, thus enabling its construction to be miniturized. But with the NAND type PLA, unfortunately, since it is constructed with the number of FETs being the same as that of the input terminals, the ON-time resistance of each of the FETs becomes larger as the input terminals are increased. As a result, its access time or time delay increases.